/*--------------------------------------------------
file name  : hvl_top.sv
created    : 2025/10/26 19:55:22
description: 
notes      : 
author     : yyrwkk
--------------------------------------------------*/
module hvl_top();

bit clk , rst_n ;

initial begin 
    clk   = 0;
    rst_n = 0;
end

initial begin 
    forever #5ns clk = ~clk;
end

initial begin 
    #($urandom_range(10,500));
    rst_n <= 1'b1;
end

initial begin 
   repeat(10) #1000_000;
   $error("timeout!");
   $finish;
end

pkt_if_wrap u_pkt_if_wrap(clk, rst_n);

`include "pkt_link.sv"

// testcase 
initial begin 
    string tc_name;
    if(!$value$plusargs ("tc_name=%s",tc_name)) $error("no tc_name!");   
    else $display("tc_name=%s",tc_name);

    if( tc_name.compare("sanity_case")) 
        tc = sanity_case::new(u_pkt_if_wrap);
    else
        $error("tc_name is invalid!");

    tc.build();
    tc.connect();
    tc.run();
    tc.report();
    $display("At %0t, [TEST NOTE]: simulation finish~~~~~~~~~~~~~~~~~~", $time);
	$finish;
end

endmodule 
